By Tertulien Ndjountche
Трёхтомный курс по цифровой электронике от издательства Wiley. В первых двух томах рассматриваются логические схемы, в третьем - конечные автоматы electronic Electronics, quantity 1: Combinational common sense Circuits (1848219849 electronic Electronics, quantity 2: Sequential and mathematics good judgment Circuits (1848219857) electronic Electronics, quantity three: Finite-state Machines (1848219865)
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Additional resources for Digital Electronics, Volume 3: Finite-state Machines
61. 37(a). The states B and D cannot be compatible because the implied NSs, C and E, are not compatible. 37(c). 50 Digital Electronics 3 The maximal compatibility classes are as follows: (AB), (AC), (AD), (AE), (BC), (CD), (DE), (ABC), (ACD) and (ADE). 37. a) Merger graph. 38, it can be deduced that the set of states (ABC) and (DE) form a closed cover. 38. 62. 62. 3. 63: – determine the compatibility classes for this machine; – construct a reduced state table. 63. 39(a) and (b) show the compatible and incompatible states, respectively.
2. 31. 32. It should be noted that the use of JK ﬂip-ﬂops results in a reduction of the number of logic gates. 18. 25. 26. 4. Variable width pulse generator The generator to be implemented has two inputs, X1 and X2 , and the output Y . The output is set to logic level 1 during a certain number of clock signal cycles; this Synchronous Finite State Machines number is speciﬁed by the bits applied to both inputs. Thus: – if X2 X1 = 01, Y = 1 for one cycle; – if X2 X1 = 10, Y = 1 for two cycles; – if X2 X1 = 11, Y = 1 for three cycles.
40, we can obtain the pairs of compatible states (AB), (AC), (AD), (BC), (BD), (BE), (CD), (CF ) and (EF ). We can also deduce that the set of states (ABCD) forms a compatibility class. As no closed polygon can be identiﬁed on the merger graph for incompatible states, we can conclude that there are only pairs of incompatible states. A choice of maximal compatibility classes that covers all the states of the state machine consists of (ABCD) and (EF ). However, the closure conditions are not satisﬁed as the set (ABCD) implies (CF ) for XY = 01 and (BE) for XY = 10.
Digital Electronics, Volume 3: Finite-state Machines by Tertulien Ndjountche